US20250286004
2025-09-11
Electricity
H01L24/08
The patent application discusses advancements in microelectronic assemblies, focusing on a die-level interposer that facilitates die-to-die fan-out scaling. This technology enables the coupling of multiple integrated circuit (IC) dies with varying pitches through hybrid bonding. The interposer features two surfaces, each connecting to different dies with distinct pitches, thus optimizing the design process and reducing the need for pre-designing each multi-die IC package.
As IC packages become more compact and complex, connecting multiple dies with different pitches poses significant challenges. Traditional methods require designing each package with a uniform pitch or accounting for pitch differences, which is both time-consuming and costly. The disclosed microelectronic assemblies address these issues by allowing more flexible design options without extensive pre-design efforts, enhancing compatibility with third-party dies.
The unique feature of the described microelectronic assembly is its ability to accommodate different die pitches using a hybrid bonded interposer. This approach is particularly beneficial for applications requiring small and low-profile components, such as computers, tablets, industrial robots, and consumer electronics like wearable devices. By enabling efficient fan-out scaling, the technology improves signal communication between dies without increasing the overall package size.
The interposer is composed of multiple layers that form a pitch translation structure. It includes a standoff layer for spacing and a routing layer for dense fan-out structures. The routing layer consists of insulating materials and conductive pathways that facilitate signal translation between different pitch sizes. These materials include various dielectrics and metals like copper and aluminum, providing robust electrical connections.
The routing layer is fabricated using back-end-of-line (BEOL) processes before hybrid bonding to the dies. It incorporates insulating materials such as silicon nitride and silicon oxide, alongside conductive pathways made from metals like copper. The thickness of the routing layer varies to accommodate different design requirements, ensuring flexibility and adaptability in multi-die configurations.