US20250287597
2025-09-11
Electricity
H10B43/35
A semiconductor device is described, featuring a plate layer and gate electrodes arranged on this layer. These gate electrodes are spaced apart in a first direction, which is perpendicular to the plate layer's upper surface. Channel holes pass through these electrodes, extending in the same direction. Within these channel holes, channel structures are present, each comprising a blocking layer, a charge storage structure, a tunneling layer, and a channel layer. This configuration enhances data storage capabilities by arranging memory cells three-dimensionally rather than two-dimensionally.
The charge storage structure within the channel holes is divided into regions: a first region adjacent to the tunneling layer and a second region between the first region and the blocking layer. The structure contains charge trap layers made of silicon nitride and barrier layers of a two-dimensional insulating material. Notably, the density of these barrier layers is higher in the first region compared to the second region, optimizing electrical characteristics and reliability.
Gate electrodes are stacked on the plate layer and spaced apart in a direction perpendicular to the plate's surface. The channel structures within these electrodes include additional components like a buried channel insulating layer. The charge storage structure here has an extra third region between the second region and the blocking layer. Barrier layers vary in thickness across these regions, being thicker in the first region than in the second, and absent in the third, further enhancing device performance.
The semiconductor device can be integrated into data storage systems. These systems include a semiconductor storage device with circuit elements and an input/output pad for electrical connections. A controller manages this setup via the input/output pad. The second semiconductor structure includes similar elements as described for individual devices, with charge trap layers of silicon nitride and barrier layers of a two-dimensional insulating material. The varying densities of these barriers across different regions contribute to improved system reliability.
Accompanying drawings provide detailed views of various embodiments of these semiconductor devices. Illustrations include plan views, cross-sectional views, and enlarged sections highlighting specific features like channel structures and gate electrode arrangements. Methods for manufacturing these devices are also depicted through schematic cross-sectional views, demonstrating steps involved in creating such advanced semiconductor configurations for enhanced data storage solutions.