MAGNETIC DEVICE AND MAGNETIC RANDOM ACCESS MEMORY

Smart overview of the Invention

The patent application describes a magnetic memory device featuring a magnetic tunnel junction (MTJ) stack with an innovative spin-orbit torque (SOT) induction wiring. This design includes a first and second terminal connected to the ends of the SOT induction wiring, alongside a selector layer linked to the first terminal. The structure is intended to enhance the performance of magnetic random access memory (MRAM), particularly focusing on improving speed and reducing power consumption.

Background

MRAM technology provides significant advantages over traditional memory types like SRAM, DRAM, and flash memory. It combines non-volatility with high speed and durability. Two primary MRAM types are spin transfer torque (STT-MRAM) and spin orbit torque (SOT-MRAM). SOT-MRAM is noted for requiring lower switching currents compared to STT-MRAM, making it a promising candidate for applications needing rapid data access and minimal energy usage.

Technical Details

The disclosed device employs an ITISIR (one transistor, one selector, one resistor) configuration to enhance cell density while minimizing the footprint and magnetic resistance. The MTJ stack comprises several layers including a free magnetic layer, a nonmagnetic spacer, and a reference layer. Additional layers like a keeper layer, hard bias layer, and optional seed or antiferromagnetic layers may be included to optimize performance.

Spin-Orbit Torque Mechanism

The SOT mechanism relies on the spin-orbit interaction effect induced by current flowing parallel to the MTJ film stack. This effect facilitates the switching of the free magnetic layer's moment either independently or in conjunction with other effects like spin transfer torque. The SOT induction wiring layer generates a spin-orbit magnetic field, which is crucial for rapidly altering the magnetic orientation of the free layer, thereby achieving faster write speeds with reduced power consumption.

Advantages and Applications

The proposed SOT-MRAM design offers significant improvements in write speed and energy efficiency, making it suitable for high-speed cache applications in CPUs and MCUs. By reducing the device footprint and enhancing cell density, this design addresses key limitations of current MRAM technologies, paving the way for more efficient memory solutions in advanced computing environments.