US20250324700
2025-10-16
Electricity
H10D64/015
The patent application describes a method for fabricating semiconductor devices, particularly focusing on non-planar transistors such as FinFETs and gate-all-around (GAA) transistors. The process involves forming a channel structure over a substrate, creating a gate structure that straddles this channel, and integrating a gate spacer with an air gap to mitigate parasitic capacitance. This innovation targets the challenges of scaling down integrated circuits while maintaining performance, particularly by addressing the RC time delay caused by parasitic capacitance in traditional designs.
The semiconductor industry has seen rapid growth through increased integration density of electronic components. Traditional methods have focused on reducing feature sizes to fit more components into smaller areas. However, as the size of components shrinks, planar transistors face limitations due to leakage currents and process variations. Non-planar transistor designs like FinFETs offer promising alternatives by providing a three-dimensional structure that enhances performance and scalability.
The described method involves several key steps: forming a channel structure along a substrate, constructing a gate structure that straddles this channel, and adding a gate spacer with an air gap. This air gap is strategically placed above the epitaxial structure and separated by the gate spacer's lateral portion. This configuration reduces parasitic capacitance, which is a crucial factor in improving the performance of non-planar transistors.
The introduction of an air gap within the gate spacer is a significant innovation aimed at reducing the dielectric constant between the gate and source/drain structures. By doing so, it minimizes parasitic capacitance and thus reduces the RC time delay, enhancing the overall performance of the transistor. This method also reduces potential damage to source/drain structures during fabrication, as the air gap is formed without direct exposure to etchants that could otherwise degrade the device.
The patent outlines a detailed method for constructing these advanced semiconductor devices, with potential applications in various types of non-planar transistors beyond FinFETs, including nanosheet and vertical transistors. The process begins with providing a substrate, forming a semiconductor fin, and then sequentially adding isolation structures, dummy gates, and spacers. The final steps include growing source/drain structures and forming the critical air gap. This method supports the creation of high-performance semiconductor devices suitable for next-generation electronics.