US20250331427
2025-10-23
Electricity
H10N50/10
The magnetic memory device features two distinct magnetic tunnel junction (MTJ) patterns on a single chip. These patterns, situated in separate regions of a substrate, are designed to enhance memory storage capabilities by providing different operational characteristics. The first MTJ pattern consists of a fixed magnetic structure, a free magnetic structure, and a tunnel barrier pattern. The second MTJ pattern includes similar components with the addition of a multiferroic pattern that exhibits both ferroelectricity and antiferromagnetism.
Modern semiconductor memory devices demand higher speed and lower power consumption. Magnetic memory devices are emerging as promising solutions due to their high-speed operation and non-volatility. The core component, the MTJ pattern, varies its resistance based on the magnetization directions of its magnetic structures. Parallel magnetization results in low resistance, while antiparallel magnetization leads to high resistance, enabling data storage and retrieval.
The inclusion of the multiferroic pattern in the second MTJ pattern is a key innovation. This pattern enhances the device's functionality by leveraging its unique ferroelectric and antiferromagnetic properties. By integrating MTJ patterns with different characteristics on a single chip, the device caters to diverse operational needs, potentially improving speed and reducing energy usage in electronic devices.
The patent outlines methods for fabricating these dual-pattern chips. Each MTJ pattern is carefully layered on designated regions of the substrate, ensuring precise placement of the fixed and free magnetic structures, tunnel barriers, and multiferroic materials. This meticulous construction process is crucial for achieving the desired electrical properties and operational efficiency.
This advanced magnetic memory device is poised to significantly impact next-generation electronics by offering improved performance metrics over traditional memory technologies. Its ability to integrate multiple operational characteristics on a single chip makes it an attractive option for various applications requiring rapid data access and minimal power consumption.