3D MEMORY DEVICE USING SELF-SELECTING MEMORY AND OPERATION METHOD OF THE 3D MEMORY DEVICE

Smart overview of the Invention

The patent application discusses a three-dimensional (3D) memory device that incorporates self-selecting memory technology. This device comprises multiple memory cells arranged in a 3D configuration on a substrate. Each memory cell includes a transistor and a self-selecting memory layer connected in series. The transistor features a channel layer parallel to the substrate's surface, while the memory layer is made of a chalcogenide-based material with Ovonic threshold switching properties.

Technical Features

The self-selecting memory layer's threshold voltage can change based on the polarity and intensity of the applied voltage. In some configurations, the transistor may include a gate electrode on the channel layer and a gate insulating layer between them. The device might also have bit lines extending perpendicular to the substrate, with memory cells arranged along these lines. Word lines intersect these bit lines and run parallel to the substrate's surface, connecting to the transistor's gate electrode.

Material Composition

The self-selecting memory layer contains a chalcogen element, possibly combined with Ge, As, or Sb, and may include Se, Te, or S. Each memory cell might feature a metal layer on one side of the memory layer or an interlayer at both ends. The 3D memory device could implement a multi-level memory system by varying the intensity of a reset pulse voltage applied to the memory layer.

Operational Method

The operation method involves selecting a memory cell by applying signals to specific bit and word lines. The device performs set or reset operations by applying a voltage equal to or greater than the memory layer's threshold voltage. A read operation uses a voltage less than or equal to the threshold voltage. Multi-level memory implementation is possible by adjusting the reset pulse voltage's intensity, with polarity variations between reset and set pulses.

Additional Considerations

The 3D memory device may include select lines to choose a specific bit line. In each memory cell, the channel layer connects to a bit line, and the gate electrode links to a word line. The described technologies provide an innovative approach to enhancing memory capacity and integration by utilizing a 3D configuration and self-selecting memory layers.