US20260026045
2026-01-22
Electricity
H10D30/6735
The semiconductor device described integrates high-performance transistors with a high degree of miniaturization. It features a substrate supporting a first and second transistor, each utilizing a two-dimensional semiconductor material for their active patterns. These transistors are interconnected by a wiring structure, allowing for enhanced electrical communication between them. The design aims to leverage the properties of two-dimensional materials to improve device performance and integration density.
The disclosure pertains to semiconductor devices employing two-dimensional semiconductor materials as channels, alongside methods for their fabrication. This approach is geared towards enhancing transistor performance by improving electron mobility and suppressing short channel effects. The use of multi-gate transistors and scalable technology is highlighted, offering improved current control without increasing gate length.
The device comprises a substrate on which a first transistor is placed, featuring a first active pattern and gate electrode. A second transistor is positioned above the first, with its own active pattern and gate electrode. A wiring structure is interposed between the two transistors, facilitating electrical connections. This configuration supports a high degree of integration and performance by utilizing two-dimensional materials for the active patterns.
The fabrication method involves forming a first etch blocking film on the substrate, followed by the sequential stacking of the first and second transistors. Each transistor is connected to a wiring structure, with the second transistor's wiring penetrating an etch blocking film to connect with the first transistor's wiring. This method ensures that the transistors maintain distinct conductive properties while being electrically interconnected.
The device includes a substrate, possibly made of silicon or other materials, with transistors stacked sequentially. Each transistor comprises an active pattern, gate electrode, and source/drain contacts. The design allows for the formation of CMOS circuits by combining transistors of different conductive types. This setup is aimed at enhancing device performance by optimizing the electrical properties of the transistors through the use of two-dimensional materials.