FERROELECTRIC FIELD EFFECT TRANSISTOR, MEMORY DEVICE, AND NEURAL NETWORK DEVICE

Smart overview of the Invention

The invention describes a ferroelectric field effect transistor (FeFET) designed to enhance memory devices and neural network devices. The FeFET comprises a channel layer, a gate electrode, and a ferroelectric layer, with an oxygen-deficient layer and a diffusion barrier layer strategically placed to optimize performance. These components work together to manage oxygen exchange and improve device stability and efficiency.

Structure and Composition

Key elements include the channel layer and the oxygen-deficient layer, both made from oxide semiconductor materials. The oxygen-deficient layer has a higher concentration of oxygen vacancies compared to the channel layer, which is crucial for device functionality. A diffusion barrier layer, potentially made from materials like silicon nitride, hafnium nitride, or aluminum nitride, is used to prevent oxygen exchange between the channel layer and the oxygen-deficient layer.

Layer Characteristics

The device features a gate intermediate layer composed of amorphous dielectric materials such as silicon oxide or silicon nitride. This layer is designed with a gradient in nitrogen and oxygen concentrations to enhance performance. The thicknesses of the various layers are carefully controlled, with the oxygen-deficient layer being thinner than the channel layer, and the diffusion barrier layer being the thinnest.

Applications

The FeFET is applicable in memory devices, offering an improved memory window and reduced channel deterioration. It is also integrated into neural network devices, where it forms part of the synaptic device array. By utilizing the unique properties of ferroelectric materials, these devices can achieve better performance in terms of speed and energy efficiency.

Design and Configuration

The configuration allows for various arrangements, such as cylindrical shapes where layers envelop each other, enhancing the structural integrity and functionality. The design ensures that the source and drain electrodes are optimally positioned in relation to the channel layer, maximizing electrical connectivity and device efficiency.