US20260051013
2026-02-19
Physics
G06T1/20
The patent application outlines a parallelized architecture designed to enhance the speed and accuracy of processing multi-dimensional data, particularly in low-latency environments such as autonomous navigation. This architecture is intended to handle large volumes of image data efficiently, surpassing the capabilities of traditional CPU and GPU processing. It aims to maintain the integrity of image feature recognition while operating at high speeds, crucial for applications requiring real-time data processing.
The invention pertains to microprocessor devices, focusing on an architecture and instruction set for multi-dimensional data processing. It emphasizes the reuse of frame data across processors and a parallelized approach to enhance performance. The need for such an architecture arises from the growing demand for processors to manage complex datasets quickly, which conventional systems struggle to achieve due to mismatched processing and data transfer speeds.
The proposed system includes multiple processors that manage frame data in parallel. It involves determining the temporal sequence of frame data and distributing it to processors configured for either two-dimensional or one-dimensional input execution. This parallel execution allows for simultaneous processing of frame data, enhancing speed and efficiency. The system can be implemented on a system-on-chip (SoC) that integrates a graphics processing unit (GPU) with multiple processors, optimizing the processing of sequential frame data.
The patent includes various figures illustrating the architecture and methods. These examples demonstrate the system's application in environments like autonomous vehicles, showcasing methods for multi-dimensional data processing and parallelization. Figures depict the computing environment, memory architecture, and processor parallelization, providing a visual understanding of the system's implementation and potential applications.
The detailed description highlights the technical benefits of the proposed solution, such as increased computational efficiency in image feature determination. By minimizing redundant data loading and utilizing multi-dimensional data processing, the architecture significantly reduces processing delays. The system employs pixel processing engines (PPEs) to handle frame data in multiple dimensions, enhancing image processing speed and responsiveness. This improvement is crucial for real-time applications, offering a hardware-level acceleration of image feature recognition tasks.