US20260096179
2026-04-02
Electricity
H10D64/518
A novel three-dimensional semiconductor device is designed to enhance both productivity and electrical performance. This device incorporates a substrate with semiconductor patterns positioned above it, spaced apart in a parallel direction to the substrate's top surface. The architecture includes a first gate pattern on the top surfaces and a second gate pattern on the bottom surfaces of the semiconductor patterns, both extending in the same direction. A bridge pattern is situated between these semiconductor patterns, contributing to the device's structural integrity and functionality.
The device features distinct elements including a gate region and an extension region within both the first and second gate patterns. The extension region of the first gate pattern uniquely protrudes below its gate region, facilitating improved connectivity and performance. The spatial arrangement ensures that the distance between the extension regions is less than that between the gate regions, optimizing the device's electrical characteristics.
The fabrication method involves forming semiconductor patterns on a substrate, followed by the creation of a bridge layer encasing these patterns. A sacrificial layer is then applied, with subsequent processes removing portions to form an interlayer insulating layer. This sequence of steps is critical for establishing the gate pattern in the newly created empty regions, ensuring precise structural dimensions and enhancing the overall device functionality.
Incorporating both memory and logic elements, the device is structured to include a memory cell array, row and column decoders, and control logic. The memory cells are three-dimensionally arranged, each linked to specific word, bit, and source lines. The row decoder selects word lines based on external address inputs, while the column decoder facilitates data paths between the sense amplifier and external devices, streamlining data processing and retrieval.
Figures accompanying the description provide a visual representation of the device's architecture. These include circuit diagrams and perspective views illustrating the spatial arrangement and integration of various components, such as the substrate, peripheral circuit structure, and cell array structure. These diagrams are essential for understanding the device's complex layout and the innovative approach to semiconductor design.