US20260150287
2026-05-28
Electricity
H10B43/20
The patent application describes a semiconductor device featuring a substrate, a patterning layer, and a channel made from a two-dimensional (2D) material. This channel is designed with a unique structure, having a relatively thin channel area and thicker contact areas. The device also includes a source electrode, a drain electrode, a gate electrode, and a gate insulating film. The invention aims to reduce contact resistance, enhancing the performance of electronic apparatuses that incorporate these semiconductor devices.
The channel's innovative design involves a flat upper surface and a lower surface closer to the substrate. The channel area is thinner compared to the contact areas, which consist of multiple stacked 2D material layers, potentially ranging from 5 to 20 layers. These materials may include transition metal dichalcogenides (TMD), graphene, black phosphorus, amorphous boron nitride, or phosphorene. The patterning layer can be made from high-k or ferroelectric materials, providing structural support and electronic properties conducive to device performance.
The manufacturing process involves forming a patterning layer and an adjustment layer, followed by depositing a 2D material precursor to create the channel. Source and drain electrodes are then formed on the channel, along with a gate electrode and insulating film. The adjustment layer, which may include materials like SiO2 or Al2O3, is designed with varying thicknesses to optimize the 2D material deposition. This method aims to enhance the device's structural and electrical characteristics by carefully controlling layer thickness and material properties.
The semiconductor device can be integrated into electronic apparatuses, such as memory devices, where it works alongside a memory controller. The design promotes reduced contact resistance, potentially improving the efficiency and performance of integrated circuits. This technology is particularly relevant for devices requiring high-density integration and low power consumption, like advanced computing and communication systems.
The patent also describes configurations with multiple vertically stacked channels, each with its own source and drain electrodes. These channels are enclosed by a gate structure, which includes a gate insulating layer and electrode, enhancing the device's electrical control. The design allows for parallel stacking of 2D material layers in both channel and contact areas, ensuring consistent electrical properties across the device. This approach supports the development of compact, high-performance semiconductor devices.