US20260181955
2026-06-25
Electricity
H10D30/6735
The semiconductor device described includes a substrate with an active region extending in one direction and a gate electrode layer that crosses this region. Multiple channel layers are positioned on the active region, spaced apart vertically and surrounded by the gate electrode layer. These channel layers enhance electrical performance by being strategically separated and stacked. Gate spacer layers are positioned on the sides of the gate electrode layer, and source/drain regions are connected to the channel layers, facilitating efficient electrical conduction.
As technology advances, the demand for high-performance, high-speed, multifunctional semiconductor devices increases. This trend necessitates the integration of finer patterns in semiconductor devices. Traditional planar MOSFETs face limitations when scaled down, prompting the development of three-dimensional channel structures like FinFETs. These structures offer improved electrical characteristics by enhancing the integration and functionality of semiconductor devices.
The device features a substrate with a first active region extending in one direction and a second active region in another. Each region has a gate structure crossing it, with multiple channel layers spaced vertically. The uppermost channel layer includes portions separated in the first direction, positioned below gate spacer layers. This configuration allows for a more efficient gate-all-around field effect transistor, enhancing the device's performance.
The patent application includes various figures illustrating the semiconductor device's design and structure. These figures provide plan views, cross-sectional views, and enlarged views to detail the device's components, such as the substrate, channel layers, gate structures, and source/drain regions. The illustrations help visualize the intricate design and arrangement of the semiconductor device's elements.
The detailed description elaborates on the semiconductor device's components, highlighting the relationships between different layers and regions. The substrate, typically made of Group IV or compound semiconductors, supports an active region defined by a device isolation layer. The active region features a fin structure, with gate structures and channel layers forming a Multi-Bridge-Channel FET (MBCFETâ„¢) structure. This design is crucial for achieving a gate-all-around field effect, optimizing the device's electrical properties.