US20260190878
2026-07-02
Electricity
H10P14/3411
The document outlines a method for manufacturing advanced semiconductor devices, specifically focusing on gate-all-around field-effect transistors (GAA-FETs). These transistors feature multiple stacked channel layers and a source/drain region. A key aspect of the method is the deposition of epitaxial layers at varying temperatures to enhance the quality and performance of the contact layers. The approach results in a contact epitaxial layer with minimal dislocations and dopant precipitates, which is crucial for the efficiency and reliability of the semiconductor device.
With the semiconductor industry moving towards smaller, nanometer-scale technology nodes, there is an increasing demand for higher device density and performance. This has led to the development of three-dimensional transistor structures like GAA-FETs, which offer improved control over the channel by surrounding it entirely with a gate electrode. This configuration helps mitigate short-channel effects and enhances device performance. As transistor dimensions continue to shrink, further innovations in GAA-FET technology are essential to meet modern semiconductor requirements.
The manufacturing process involves forming a first epitaxial layer over the source/drain region at a high temperature, followed by a second epitaxial layer at a temperature 20% to 30% lower than the first. This temperature control is critical for reducing defects and improving the structural integrity of the contact layers. The epitaxial layers are designed to be substantially free of dopant precipitates and have fewer than 50 dislocations, each measuring between 1 nm to 40 nm and oriented at specific angles relative to crystallographic planes.
The semiconductor device features a gate electrode layer that surrounds multiple channel layers, providing comprehensive control over the channel. Source and drain features are positioned at the ends of these channel layers, with contact epitaxial layers enhancing conductivity. These layers are heavily doped to match the conductivity of the metallic contacts, reducing electrical resistance. A contact etch stop layer and inner spacer features made of dielectric materials are also incorporated to further optimize device performance.
The source and contact epitaxial layers can be either n-type or p-type doped, depending on the specific application. For n-type layers, silicon or SiGe with phosphorous doping is used, while p-type layers might use a SiGe alloy with boron doping. The doping concentrations are carefully controlled to ensure optimal electrical properties. Inner spacer features are constructed from various silicon-based dielectric materials, some with low dielectric constants to improve device isolation and performance.