PROCESSOR, SYSTEM AND METHOD PROVIDING LOW PRECISION NUMBER MATRIX MULTIPLICATION

Smart overview of the Invention

The patent application describes a processor designed to perform matrix multiplication using low bit fixed point formats. It encodes matrix weights into 1-bit or 2-bit formats and performs matrix multiplications using these encoded weights, followed by result accumulation. Supported formats include symmetric binary, asymmetric binary, ternary, and quaternary. The processor employs operations like XNOR, AND, or 2-bit multipliers for multiplication and higher precision for accumulation, rounding results back to low-bit formats. This approach significantly enhances neural network inference efficiency, offering a 2-4× performance gain over conventional 4-bit formats.

Claim of Priority

This application claims priority to German Patent Application No. 102025147502.4, filed on November 17, 2025, and its parent application No. 102025100111.1, filed on January 3, 2025. Both applications are entitled "PROCESSOR, SYSTEM AND METHOD PROVIDING LOW PRECISION NUMBER MATRIX MULTIPLICATION" by Sven Woop, et al. The entire contents of these prior applications are incorporated by reference.

Field of the Disclosure

The disclosure pertains to data processing, specifically involving a general-purpose graphics processing unit (GPU) for matrix multiply-accumulate (MMA) operations using low precision fixed point numbers. It targets neural network operations within artificial intelligence applications, addressing computational challenges in efficiently training and inferring large neural networks that demand significant resources.

Background of the Disclosure

Artificial Intelligence (AI) and neural networks have revolutionized fields like computer vision and natural language processing. However, the computational demands of large networks have increased power consumption and memory needs. This is particularly challenging for resource-constrained devices. The invention aims to address these issues by developing processors and methods optimized for efficient matrix multiplication operations, crucial for neural network processing.

System Overview

The described computing system includes a processing subsystem with processors and memory, communicating via an interconnection path. It supports parallel processing with a GPU that accelerates graphics and machine-learning operations. The system can be configured in various architectures, such as a system on chip (SoC) or system in package (SIP). Communication paths use protocols like PCI Express and NVLink, enabling efficient data transfer across components. The system supports integration with other devices, enhancing its versatility for different applications.