TESTING INTEGRATED CIRCUITS VIA SCAN CHAIN COMPRESSION

Smart overview of the Invention

The patent application describes a method for testing integrated circuits (ICs) using scan chain compression. This method involves generating a compactor via explicit expander graph construction and integrating it with a decompressor within a device-under-test (DUT). A compressed test pattern is fed into the DUT and expanded into internal scan-ins by the decompressor. The resulting scan-out data is then compressed into output vectors by the compactor. These vectors are compared to expected outputs to determine the DUT's pass/fail status.

Technical Field

This invention pertains to chip testing, specifically focusing on integrated circuit testing through scan chain compression. Scan chains, which are series of flip-flops forming a shift register, are commonly used for IC testing. As ICs grow more complex, the number of flip-flops increases, making testing slower and more costly due to the greater volume of test patterns and data bits required. Scan chain compression addresses this by reducing the test data volume and testing time while maintaining fault coverage.

Components and Challenges

Scan chain compression utilizes two main components: a decompressor and a compactor, both embedded within the chip being tested. The decompressor converts compressed input test patterns into internal scan-ins, while the compactor compresses scan-out data into fewer bits for output. Conventional compactors face challenges with unknown values (Xs) in circuits, which can corrupt test signatures and mask scan chains. Various X-blocking techniques exist but have limitations.

Innovative Approach

The invention presents a novel approach using expander graphs to generate a compactor, improving X-tolerance and compression efficiency. This method involves creating a bipartite graph between internal scan channels and external scan-out pins, ensuring no two rows in a hash table share the same binary representation. This approach minimizes unknown Xs and meets expander graph criteria, enhancing the compactor's performance in scan chain compression.

System Implementation

The chip testing system includes a controller and a hold-toggle circuit, managing operational modes and hold-toggle patterns during testing. The DUT, equipped with a decompressor and compactor, processes compressed test patterns and produces compressed output vectors. These vectors are evaluated against desired outputs stored in the testing system's memory to ascertain the DUT's pass/fail status. Expander graphs, characterized by strong connectivity and sparse edges, form the basis of the compactor's design, ensuring efficient and reliable IC testing.