MEMORY DEVICE HAVING THREE-DIMENSIONAL STRUCTURE AND METHOD OF OPERATING THE SAME

Smart overview of the Invention

The memory device detailed in the patent application features a three-dimensional structure that enhances data storage capacity and operational reliability. It comprises a peripheral circuit structure and a cell array structure positioned above it. The cell array structure includes vertically spaced gate electrodes and a channel layer made of an oxide semiconductor, which passes through these electrodes. This design allows for increased integration of memory cells, which are essential for storing large amounts of data in electronic systems.

Key Components

The cell array structure consists of several key layers within a vertical opening. These include a back-side electrode layer situated on the channel layer's side wall, and a conductive interfacial layer positioned between the channel layer and the back-side electrode layer. Additionally, a bit line pad is strategically placed on the channel layer's side wall but is separated from the back-side electrode layer in the vertical direction. These components work together to form the core of the memory device's three-dimensional structure.

Operation Method

The method of operating this memory device involves a series of steps to ensure efficient functionality. The memory cell array comprises multiple memory cell strings, each connected to a bit line and a common source line. The operation includes erasing memory cell strings by applying specific voltages to the word line and back-side electrode line, while floating the bit line. This approach helps in maintaining the reliability and performance of the memory device during operations such as erasing, programming, and reading.

Enhanced Features

The memory device includes additional features to improve its functionality. A spacer insulating layer is introduced between the back-side electrode layer and the bit line pad, enhancing isolation. The device also incorporates a common source line connected to the channel layer and connection vias linked to both the common source line and the back-side electrode layer. These enhancements contribute to the device's improved operational characteristics and integration capabilities.

Applications and Benefits

This memory device is designed for electronic systems requiring high data storage capabilities. Its three-dimensional structure allows for higher integration of memory cells, leading to increased storage capacity and improved operational reliability. The innovative design and operating methods offer significant advantages in terms of data storage efficiency, making it highly suitable for advanced computing applications.