US20260214911
2026-07-23
Electricity
H10B63/845
The patent outlines a vertical nonvolatile memory device, which includes a sophisticated structure of memory cells designed to improve data retention and integration. The device features a stack of alternating gate electrodes and spacers, a channel layer, and a charge storage layer. The charge storage layer is composed of a matrix embedded with nanostructures, each having a core-shell configuration with distinct dielectric materials. This structure aims to enhance the performance of nonvolatile memory devices by optimizing data reliability and operational speed while minimizing power consumption.
The charge storage layer is pivotal in the device's architecture, consisting of a matrix and nanostructures that are distributed discontinuously within it. Each nanostructure includes a core made of a first dielectric material and a shell of a second dielectric material, both differing from the matrix's third dielectric material. The third material is amorphous with a higher bandgap than the first material, thus contributing to the device's efficiency. The dielectric materials used in the core and shell include various oxides, while the matrix may consist of oxides, oxynitrides, or nitrides.
The first dielectric material in the core can include oxides of elements like hafnium, titanium, and zirconium, among others. The second dielectric material, forming the shell, is an oxide different from the first, potentially including similar elements. The third dielectric material, comprising the matrix, may include oxides, oxynitrides, or nitrides of elements such as aluminum and silicon. The nanostructures have a cross-sectional diameter of 10 nm or less, and their spacing is maintained to optimize performance.
The device's design ensures that the nanostructures are spaced appropriately within the matrix, maintaining a specific isoperimetric ratio and volume distribution of materials. The charge storage layer features surfaces with minimal roughness, enhancing the device's reliability. Additionally, each memory cell string includes a charge blocking layer and a charge tunneling layer, further refining the memory device's operational capabilities. The arrangement of these layers ensures efficient charge storage and retrieval.
The manufacturing method involves stacking gate electrodes and insulating spacers in a specific configuration, followed by forming a channel hole and depositing the charge storage and channel layers. The charge storage layer is created by forming a mixture layer within the channel hole, which is then heat-treated to develop the matrix and nanostructures. This process ensures the distinct distribution of materials and the formation of the desired core-shell structures, optimizing the device's performance and integration capacity.