US20260214932
2026-07-23
Electricity
H10D30/62
The patent application introduces a semiconductor device with innovative gate structure configurations and a fabrication method. The device comprises a fin structure on a substrate, a nanostructured channel region atop the fin, and a gate-all-around (GAA) structure encircling the channel. The GAA structure features a high-K (HK) gate dielectric layer with a doped metal region, a p-type work function metal (pWFM) layer, a bimetallic nitride layer, an n-type work function metal (nWFM) layer, and a gate metal fill layer. These elements work together to optimize the device's performance.
In response to the growing demand for higher performance and lower costs in semiconductor technology, the industry has been scaling down device dimensions like MOSFETs and finFETs. This miniaturization has increased the complexity of manufacturing processes. The application addresses these challenges by presenting a method to create semiconductor devices with varied threshold voltages on a single substrate, enhancing multi-functional capabilities.
The application details various embodiments to implement the proposed technology. The focus is on forming features in direct contact or with additional features between them. Spatial terms describe the orientation of elements, adaptable to different device orientations. Definitions are provided for terms like "high-k," "low-k," "p-type," and "n-type," crucial for understanding the materials and processes involved.
The proposed method allows the creation of multi-threshold voltage (multi-Vt) devices by adjusting the thickness and composition of FET gate structures. This is achieved without changing the work function metal layer material or thickness, offering a cost-effective and time-efficient solution. The method involves forming PFETs with varying metal concentrations in the HK gate dielectric and bimetallic nitride layers, resulting in different effective work function (EWF) values and threshold voltages.
By tuning metal concentrations, the invention enables precise control over the EWF values and threshold voltages of PFETs. This adjustment is possible without altering the WFM layer's material or thickness, facilitating the creation of devices with smaller dimensions and enhanced performance. The method promises significant cost and time savings, making it a valuable advancement in semiconductor device manufacturing.