US20260252662
2026-08-27
Physics
G06F17/16
The patent application describes a processor designed for efficient parallel matrix computations, specifically cross-product matrix multiplication. The processor features vector registers to store sub-matrices from two source matrices and execution circuitry to handle the multiplication process. A decoding mechanism interprets instructions that specify the source matrices and the desired operations. The execution circuitry then multiplies combinations of sub-matrices to produce four sub-matrices of a resulting matrix, which are stored in a third vector register.
Matrix multiplication is a fundamental operation in various computational fields, including graphics processing and machine learning. Traditional matrix processing instructions have limitations in terms of computational efficiency, especially as data processing demands grow. The invention addresses these challenges by introducing new instructions and microarchitectures to enhance performance for high-demand tasks.
The processor can be a general-purpose or special-purpose processor, such as those used in machine learning or graphics processing. It supports various architectures, including complex instruction set computing (CISC) and reduced instruction set computing (RISC). The processor may include integrated circuits or semiconductor dies and can execute instructions received via an interface connected to memory or other storage.
Instructions for matrix multiplication specify source matrices and the operations to be performed. These instructions can indicate matrices stored in vector registers or memory locations. The processor's vector registers can vary in size, accommodating different matrix dimensions and data element sizes. The instruction format includes fields for operation codes, source, and destination operands.
The processor supports various data element sizes, ranging from 2-bit to 32-bit, allowing flexibility in matrix representation. For example, 8-bit data elements can be signed or unsigned integers or floating-point formats like bfloat8 and hfloat8. The processor can handle different combinations of data types across matrices, enhancing its versatility for diverse computational tasks.