US20260276704
2026-09-17
Physics
G01R31/31705
The patent application describes an innovative approach to integrating chiplets within an integrated circuit package using a unified test and debug architecture. Chiplets are smaller, modular semiconductor components that perform specific functions such as processing or memory. These components are connected via a package interconnect, specifically using a Universal Chiplet Interconnect Express (UCIe) protocol. This setup allows for seamless communication and interoperability among chiplets from different vendors, enhancing flexibility and cost efficiency in IC design.
The architecture features a unified test and debug system that facilitates the transmission of debug messages between and within chiplets. A designated chiplet, known as the package debug endpoint, serves as the link endpoint for off-package communication, such as a PCIe link. Debug messages can be routed through this endpoint, enabling comprehensive testing of the chiplet functionalities using a common protocol. This setup allows for effective integration and testing of chiplets from diverse manufacturers within the same package.
The architecture includes an interface-agnostic external hardware debug interface. This interface supports various protocols, allowing debug messages to be sent as UCIe packets. These packets can be tunneled through multiple test and debug interface solutions, including JTAG, I2C, USB, and others. Such flexibility ensures that upper-layer test and debug software remains reusable across different implementations, enhancing the efficiency of the testing process.
Components within the chiplet architecture are described as "communicatively coupled," meaning they can send or receive signals through wired or wireless communication media. This coupling supports a wide range of signal types, facilitating robust communication between integrated circuit dies within a package or between components on a printed circuit board. The architecture supports both direct and indirect coupling, ensuring versatile connectivity options.
The disclosed embodiments are adaptable, capable of being implemented in hardware, firmware, software, or combinations thereof. The architecture is designed to accommodate modifications and alternatives, ensuring broad applicability across different use cases. The patent emphasizes the flexibility of the architecture, allowing it to be practiced without specific details while covering all potential modifications and equivalents within the scope of the claims.