SEMICONDUCTOR STRUCTURE HAVING VERTICAL CONDUCTIVE GRAPHENE AND METHOD FOR FORMING THE SAME

Smart overview of the Invention

A semiconductor structure is developed by integrating vertical conductive graphene, enhancing the electrical interconnects in integrated circuits (ICs). This method involves creating an interconnect opening in a dielectric layer to expose a contact feature on a substrate. A metal layer is then formed over the dielectric layer, followed by the deposition of a graphene conductive structure. This graphene structure fills the interconnect opening, establishing an electrical connection with the contact feature and orienting perpendicularly to the substrate.

Background

The semiconductor IC industry is advancing rapidly, with newer generations of ICs featuring smaller and more complex circuits. Techniques like the Damascene process are crucial for forming back-end-of-line (BEOL) interconnect structures, which are vital for the miniaturization and performance of ICs. The development of improved interconnect structures remains a focal point in the industry to meet the demands of modern IC design.

Detailed Process

The process begins by providing a substrate with a conductive feature. A dielectric layer is deposited on this substrate and patterned to create a through hole. A barrier/liner layer and a conductive structure are formed over the dielectric layer, filling the through hole. This conductive structure is then patterned to form the desired interconnect structure, which may include various semiconductor materials and doping techniques to enhance performance.

Materials and Techniques

The substrate used may be an elemental or compound semiconductor, such as silicon or gallium arsenide, and can include multilayer structures or non-semiconductor materials. A dielectric layer is formed over the substrate, often using materials like silicon dioxide or phosphosilicate glass, and is patterned to create interconnect openings. Techniques like chemical vapor deposition (CVD) and photolithography are employed to achieve precise patterning and material deposition.

Patterning and Etching

A photoresist is used to pattern the dielectric layer, which is exposed to radiation through a mask to transfer the desired layout. The photoresist undergoes a series of processes, including baking, exposure, and development, to reveal the areas to be etched. Anisotropic etching techniques, such as reactive ion etching (RIE), are used to precisely etch the dielectric layer, ensuring vertical alignment and minimal horizontal etching, crucial for creating effective interconnect structures.