US20260304889
2026-10-01
Electricity
H10D64/251
The patent application describes an integrated circuit design utilizing a standard cell architecture that leverages both frontside and backside connections along with power vias. This design aims to improve power delivery to the circuit by providing flexible power rail options. The standard cell can include configurations of two transistors, typically one n-channel and one p-channel device, or more complex arrangements like NAND or NOR gates with four transistors. The innovative use of power vias at the boundaries of the cell layout facilitates these connections.
As the size of integrated circuits continues to decrease, maintaining efficient power delivery and connectivity becomes challenging. The reduction in gate lengths and pitch scaling between devices complicates the inclusion of vias necessary for connecting frontside and backside interconnects. This architectural approach addresses these challenges by offering a solution that accommodates high-density layouts without sacrificing power delivery efficiency.
The standard cell layout is versatile, supporting various transistor technologies, particularly gate-all-around (GAA) and forksheet configurations. Each transistor within the cell can include multiple nanoribbons or semiconductor bodies, enhancing the design's adaptability. The layout allows for both frontside and backside power compatibility, crucial for accommodating different design rules and ensuring efficient power distribution across the circuit.
The integrated circuit design includes a first and second semiconductor region, each extending in a specified direction and connected by a gate structure orthogonally. Conductive vias extend through the dielectric layers to connect topside contacts with backside conductive layers, facilitating power routing. This configuration allows power vias to align with conductive layers along the cell boundaries, ensuring seamless integration with both frontside and backside connections.
The described techniques can be applied to various non-planar transistors, such as finFETs, nanowires, and nanoribbons. The architecture supports different gate formation processes and semiconductor materials, offering flexibility for diverse applications. By addressing the challenges of power delivery in scaled-down integrated circuits, this architecture provides a robust solution for modern semiconductor device fabrication.